Read Only One Side of Boolean Expression and

Boolean Function

endline – a Boolean function which is true when no more than data tin can be read

From: VHDL 101 , 2011

Boolean algebra

B. HOLDSWORTH BSc (Eng), MSc, FIEE , R.C. Wood MA, DPhil , in Digital Logic Design (Quaternary Edition), 2002

ii.13 Consummate sets

Whatsoever Boolean function can exist implemented using only AND and INVERT gates since the OR function can be generated by a combination of these two gates, as shown in Effigy 2.20(a). It follows that these two gates can implement whatsoever arbitrary Boolean function and they are said to form a complete fix. Similarly, the OR and Capsize gates besides class a complete set since the AND function can be implemented past a combination of these two gates, as shown in Effigy 2.20(b).

Effigy two.twenty. Consummate sets (a) OR/Invert (b) AND/INVERT

The derived gates NAND and NOR are in themselves a complete set since, for example, a series combination of ii NAND gates will generate the AND function [Figure two.21(a)]. In this connectedness the second NAND gate has all its inputs commoned and acts every bit an inverter. Similarly, the OR function can be generated by two NOR gates in serial (Effigy two.21(b)), where the 2nd NOR gate is implementing the inversion function. It follows that whatever arbitrary Boolean function tin can be implemented by either of these gates.

Effigy 2.21. Complete sets formed by (a) serial combination of two NAND gates and (b) serial combination of ii NOR gates

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From Nil to One

Sarah 50. Harris , David Harris , in Digital Design and Computer Architecture, 2022

1.5.6 Multiple-Input Gates

Many Boolean functions of three or more inputs exist. The most common are AND, OR, XOR, NAND, NOR, and XNOR. An Northward-input AND gate produces a TRUE output when all North inputs are TRUE. An N-input OR gate produces a Truthful output when at least 1 input is TRUE.

Example ane.16

Three-Input NOR Gate

Figure ane.19 shows the symbol and Boolean equation for a three-input NOR gate. Complete the truth table.

Effigy 1.19. Iii-input NOR gate

Solution

Figure 1.20 shows the truth table. The output is TRUE merely if none of the inputs are True.

Figure 1.xx. 3-input NOR truth table

Effigy 1.21. Four-input AND gate

Figure ane.22. Four-input AND truth table

Example i.17

4-Input And Gate

Figure one.21 shows the symbol and Boolean equation for a four-input AND gate. Create a truth table.

Solution

Figure ane.22 shows the truth tabular array. The output is TRUE only if all of the inputs are Truthful.

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Logic gates

Huw Fox , Nib Bolton , in Mathematics for Engineers and Technologists, 2002

Problems 8.iii

1

Country a Boolean part that can exist used to represent each of the switching circuits shown in Figure viii.32.

Figure 8.32. Problem 1

2

Give the truth tables for the switching circuits represented by the Boolean functions:

(a) $\left(a+\overline{b}\right)+\left(a+\overline{c}\right),$ (b) $\overline{a}\cdot \left(a\cdot b+\overline{b}\right)\cdot \overline{b}$

three

Make up one's mind the Boolean functions that could generate the outputs in Figure 8.33.

Figure viii.33. Trouble three

4

Give the truth table for the switching circuit corresponding to the Boolean part:

$\left(a\cdot \overline{b}\right)+\left(\overline{a}\cdot b\right)$

5

Draw switching circuits to represent the following Boolean functions:

(a) $a\cdot \left(a+b\right),$ (b) $a\cdot \left(a\cdot b+c\right),$ (c) $a\cdot \left(a+\overline{b}\cdot \left(a+c\right)\right)$

6

Make up one's mind the Boolean equations describing the logic circuits in Figure 8.34, and so simplify the equations and hence obtain simplified logic circuits.

Figure 8.34. Trouble half dozen

7

Describe switching circuits to represent the Boolean functions:

(a) $a\cdot b,$ (b) $a\cdot b+b,$ (c) $c\cdot \left(a\cdot b+a\cdot \overline{b}\right),$ (d) $a\cdot \left(a\cdot b\cdot \overline{c}+a\cdot \left(\overline{b}+c\right)\right).$

8

Derive the Boolean functions for the truth tables in Table 8.21(a) and (b).

Tabular array eight.21(a).

a	b	c	Function
0	0	0	0
0	0	one	1
0	1	0	0
0	1	1	0
one	0	0	0
1	0	one	0
1	1	0	1
1	1	one	0

Table viii.21(b).

a	b	c	Office
0	0	0	0
0	0	1	0
0	one	0	0
0	1	ane	1
one	0	0	0
1	0	1	0
1	1	0	0
1	ane	i	1

9

Determine the Boolean equations describing the logic circuits in Effigy viii.35, then simplify the equations and hence obtain simplified logic circuits.

Effigy 8.35. Problem eight

10

For the Karnaugh maps in Figure 8.36, produce the simplified Boolean expression.

Figure 8.36. Trouble 10

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Combinational logic circuits

John Crowe , Barrie Hayes-Gill , in Introduction to Digital Electronics, 1998

Minimised class

The about complex Boolean part in the excursion is the one for C _out since it depends on all of the nine inputs. The minimised expression for C _out contains over 30 essential prime number implicants, which means that this many AND gates plus an OR gate with this number of inputs would be needed for a minimised two-level implementation. Furthermore, some of the input variables (or their complements) must exist fed to upwards to xv of the 31 essential prime implicants.

Clearly the large number of gates required, the big number of inputs they must possess, and the fact that some signals must feed into many gates, means that this implementation is besides impractical, although it is an improvement on the fundamental ii-level form. So although the ii-level implementation is theoretically the fastest (assuming ideal gates) nosotros see that for this application it is non really applied.

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Combinational logic design with MSI circuits

B. HOLDSWORTH BSc (Eng), MSc, FIEE , R.C. Forest MA, DPhil , in Digital Logic Design (Fourth Edition), 2002

5.half-dozen Multi-level multiplexing

The implementation of Boolean functions may be achieved more economically and with fewer interconnections past using more than i level of multiplexing. Using the method described in the previous instance for the part

$f(A,B,C,D)=\sum 0,1,2,5,7,\mathrm{nine},15,\text{tin can't happen terms}\mathrm{iv},11,\mathrm{thirteen}$

the residue functions are found to be

$d_0=d_2=1,d_{\mathrm{five}}=d_6=0,d_{\mathrm{three}}=d_4=d_{\mathrm{vii}}=D,d_{\mathrm{one}}=\overline{D}$

assuming A, B and C have been chosen equally the selection variables. The implementation of the function using an 8-to-ane MUX is shown in Figure 5.9. A typical 8-to-one MUX that could be used in this design is the 74251. This is a 16 pin device having 8 data inputs, three option inputs, true and complemented outputs and a strobe line non shown in Figure 5.9 which would be held at logic 0 level.

Figure 5.9. Example of multi-level implementation of a 4 variable function (a) and (b) single-level (c) and (d) 2-level and (e) iii-level

To implement the aforementioned function using two levels of multiplexing, a 4-to-1 multiplexer M5 is used to generate the function output. The function and the 'can't happen' terms are listed in the left-hand column of Figure 5.nine(c). The selection variables for the output MUX are C and D and the variables A and B form the residue functions required at the four inputs.

The starting time level of multiplexing will consist of four two-to-1 multiplexers, each of them having B as the select variable. Their inputs can exist determined by examining the listings in each of the four right-hand columns in Effigy v.9(c). For the cavalcade headed $\overline{C}$ $\overline{D}$ there are two terms, Ā $\overline{B}$ and the 'can't happen' term ĀB. When the pick variable B = 0, the required input is Ā and when the selection variable B = i, the required input is 0 since ĀB is a 'can't happen' term. The starting time level inputs obtained from the 3 remaining columns of Figure 5.9(c) are marked on the function implementation diagram shown in Figure 5.9(d). It is immediately apparent from an inspection of this diagram that multiplexers M2, M3 and M4 are redundant. The number of interconnections required is ten and an inverter for the variable A may be required. Two multiplexer packages are needed, neither of them being fully utilised; this may or may not exist a disadvantage as far equally space requirements are concerned.

Information technology is also possible to implement the part using iii levels of multiplexing. For this organisation the conventional compages requires four 2-to-1 multiplexers at the first level, ii at the 2nd level and one at the output level although some of these multiplexers may exist found to be redundant prior to implementation. The technique used to notice the MUX inputs at the first level is identical to that used for ii level multiplexing. It consists of showtime finding the residue functions at the inputs to the output and 2d level multiplexers and finally determining the input residuum functions at the showtime level from the second level listings. Implementation of the function using three levels of multiplexing is shown in Figure 5.9(due east). The remainder functions at each level of multiplexing are marked on the diagram and it volition be observed that M2, M3, M4 and M5 are redundant. The implementation requires a single quad 2-to-ane MUX and an inverter if the complement of variable A is not available. The number of pin connections used for this implementation is ten, but only one multiplexer package is needed. In general the possibility of redundancy in a multi-variable office is highest when the smallest multiplexer elements are used.

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Behavioral coding function I: blocks, variables, and operators

Ronald Mehler , in Digital Integrated Circuit Design Using Verilog and Systemverilog, 2015

Reduction operators

Reduction operators also perform Boolean functions but are unary, which is to say that they only operate on a single operand. They produce a single-flake output regardless of the size of the input operand. Their symbols are shown in Table iii.fifteen, and some examples of their usage are shown in Figure 3.35. These operators are commonly used for parity generators and to detect a maximal value of a variable. OR reduction can equally easily be used to detect that a variable either is or is not all zeros, just at that place are other, more intuitive means of doing that.

Tabular array three.15. Reduction operators

Symbol	Operation
&	AND reduction
∼&	NAND reduction
|	OR reduction
∼|	NOR reduction
^	XOR reduction
∼^ or ^∼	XNOR reduction

Figure 3.35. Reduction operators

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Karnaugh maps and part simplification

B. HOLDSWORTH BSc (Eng), MSc, FIEE , R.C. Forest MA, DPhil , in Digital Logic Pattern (Fourth Edition), 2002

3.4 Boolean functions of two variables

In that location are a specific number of Boolean functions of ii variables. Each Boolean office in its canonical grade will consist of a certain number of minterms; for example, $f(A,B)=\overline{A}B+A\overline{B}$ is a Boolean function of two variables and contains ii of the 4 available minterms. The total number of Boolean functions of two variables can be obtained in the following mode.

Figure iii.two shows a table in which the presence of a minterm in a 2-variable function is indicated past a 1, and its absence past a 0. For case, if the minterm $\overline{A}\overline{B}$ is included in the expression, its presence volition be represented by a 1 in the position of that minterm in the table. If not included, its absence volition exist indicated by a 0. In the example where all four minterms are absent, this will be indicated by a column of four 0s, as shown in the table, and it follows that the corresponding Boolean function will be f ₀ = 0.

Figure iii.2. Table for determining all the Boolean junctions of two variables

There are 2 means in which the entry in the first row can be allocated: it can be either 0 or 1. There are also 2 means in which the entry in the second row can exist allocated. When combined with the offset row allocation this leads to four ways in which the first two rows tin can be allocated with 0s and 1s. For four rows, it follows that there are two^iv = 16 ways in which the 0s and 1s tin can be allocated. These allocations are shown in Figure three.2 and the 16 Boolean functions of two variables can be written down immediately from this table and are tabulated in Figure 3.3

Effigy 3.3. The xvi Boolean functions of ii variables

Equally the number of variables increases, the number of Boolean functions that tin can be formed increases quickly. For iii Boolean variables there are 2^eight = 256 possible Boolean functions, for four variables at that place are two^xvi = 65 536 possible Boolean functions and for northward variables there are two⁽²ⁿ⁾ possible Boolean functions.

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Combinational logic pattern principles

B. HOLDSWORTH BSc (Eng), MSc, FIEE , R.C. WOODS MA, DPhil , in Digital Logic Pattern (Fourth Edition), 2002

4.8 NOR logic implementation of sums-of-products

It often happens that a Boolean function is expressed as a sum of production terms (sometimes, but not necessarily, minterms) and if this function is to exist implemented using NOR gates and then it must get-go be converted to the product-of-sums form. For example, suppose that it is required to implement, using only NOR gates, the function

$f=\sum 0,\mathrm{one},3,\mathrm{four},5,\mathrm{viii},12,13,\mathrm{fifteen.}$

The absent minterms in this summation represent the changed function, $\overline{f}$ , and are plotted as 0s on the K-map shown in Effigy iv.10(a). Simplifying,

Effigy 4.ten. NOR implementation of a sum-of-products expression (a) Plot of the inverse part (b) Implementation of minimised product-of-sums expression

$\overline{f}=C\overline{D}+\overline{A}BC+A\overline{B}D.$

Hence, by De Morgan's theorem,

$f=(\overline{C}+D)(A+\overline{B}+\overline{C})(\overline{A}+B+\overline{D}).$

This is the minimal product-of-sums form of the original Boolean function and it is shown implemented using NOR gates in Effigy iv.10(b).

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Combinational Logic Blueprint

Sarah L. Harris , David Harris , in Digital Pattern and Estimator Architecture, 2022

2.2.3 Product-of-Sums Form

An alternative way of expressing Boolean functions is the product-of-sums (POS) canonical form. Each row of a truth table corresponds to a maxterm that is FALSE for that row. For example, the maxterm for the first row of a two-input truth table is (A + B) because (A + B) is FALSE when A = 0, B = 0. We tin write a Boolean equation for any excursion straight from the truth table as the AND of each of the maxterms for which the output is Imitation. The product-of-sums canonical form can also exist written in pi notation using the product symbol, Π.

Case 2.3

Production-of-Sums (POS) Form

Write an equation in product-of-sums form for the truth table in Figure 2.13.

Figure 2.13. Truth table with multiple FALSE maxterms

Solution

The truth tabular array has two rows in which the output is FALSE. Hence, the part can be written in product-of-sums form equally $\mathrm{Y}=(A+B)(\overline{A}+B)$ or, using pi notation, $\mathrm{Y}=\mathrm{\Pi }\left(M_0,{\mathrm{Grand}}_2\right)$ or $\mathrm{Y}=\mathrm{\Pi }(0,2)$ . The first maxterm, (A + B), guarantees that Y = 0 for A = 0, B = 0, considering whatsoever value AND 0 is 0. Likewise, the 2d maxterm, $\left(\overline{A}+B\right),$ guarantees that Y = 0 for A = 1, B = 0. Figure 2.13 is the same truth table as Figure 2.9, showing that the aforementioned function can be written in more than one style.

Similarly, a Boolean equation for Ben's picnic from Figure ii.10 tin be written in product-of-sums grade by circling the three rows of 0's to obtain $\mathrm{Due\; east}=(A+\overline{R})(\overline{A}+R)(\overline{A}+\overline{R})$ or $\mathrm{E}=\mathrm{\Pi }(\mathrm{one},\mathrm{ii},\mathrm{iii})$ . This is uglier than the sum-of-products equation, $E=\overline{A}\overline{R}$ , but the two equations are logically equivalent.

Sum-of-products produces a shorter equation when the output is Truthful on merely a few rows of a truth table; production-of-sums is simpler when the output is FALSE on but a few rows of a truth able.

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A Survey on Zero-Knowledge Proofs

Li Feng , Bruce McMillin , in Advances in Computers, 2014

four.6 ZKP Sketch for Saturday

The quadratic residuosity problem is the question of distinguishing past calculating the quadratic residues modulo n, where n is a composite number of two odd primes p and q. Nether the assumption of quadratic residuosity that 2 states are computationally indistinguishable through the calculation of the quadratic residues modulo north, a protocol for satisfiability (SAT) is suggested that directly simulates a circuit that evaluates given instances of SAT [29].

The general technique in Ref. [xviii] is through the simulation of an arbitrary Boolean circuit without disclosing the inputs or any intermediary results. At the terminate of the protocol, if the final output of the circuit is one, and so the excursion is satisfiable, but cypher else.

Let u  = b ₁, b ₂,…, b_k be a g bit string of the prover. For each 1   ≤ i  ≤ g, let z_i and z′ _i be the two encryptions of b_i randomly chosen past the prover. It is easy for the prover to convince the verifier that the k scrap strings encrypted by z _one, z ₂,…, z_thousand and z′_one, z′₂,…, z′ _m are identical without providing the verifier with any additional information by the following string equality protocol.

Definition 2.eleven (String Equality Protocol) For each i, 1   ≤ i  ≤ k, the prover gives the verifier some x _i   ∈ ℤ _⋉ ^⁎ (cogent the set of integers relatively prime to n between 1 and due north  −   1) so that z _i z _i ^′  ≡ 10 _i ²(modernistic   n).

Definition two.12 (Boolean Computation Protocol) Consider any Boolean role B : {0, 1} ^t   →   {0, 1} agreed upon between the prover and the verifier, and any bits b _one, b ₂,…, b_t only known to the prover. For one   ≤ i  ≤ t, let z_i be an encryption of b_i known to the verifier. Allow b  = B (b ₁, b _two,…, b_t ). The prover produces an encryption z for b and convinces the verifier that z encrypts the correct bit without giving the verifier any information on the input bits b ₁, b ₂,…, b_t nor on the result b.

A permuted truth table for the Boolean function B is introduced here, which is a binary string of length (t  +   one)2 ^t formed of 2 ^t blocks of t  +   i bits. The concluding bit of each block is the value of B on the other t bits of the cake. Let s exist the number of permutations agreed upon between the prover and the verifier:

1.

P: The prover randomly chooses s permuted truth tables for B and discloses encryptions for each of them.

2.

V: The verifier selects a random subset X  ⊆   {ane, 2,…, s} and sends information technology to the prover as a claiming.

iii.

P: The prover chooses 1 of the following options based on the request from the verifier:

•

For each j ∈ 10, the prover opens the entire encryption of the jth permuted truth table.

•

For each j ∉ X, the prover points to the advisable block in the encryption of the jth permuted truth tabular array and uses the post-obit string equality protocol to convince the verifier that z ₁, z ₂,…, z_tz encrypts the same bit string as this block.

4.

5: The verifier makes the following verifications:

•

The verifier checks if it is a valid truth table for B.

•

The verifier checks if z ₁, z ₂,…, z_tz encrypts the aforementioned bit cord.

Effigy 2.10 illustrates the ZKP for Boolean ciphering.

Effigy 2.10. ZKP for Boolean computation

Based on the above discussions, a ZKP sketch has been designed for SAT. f : {0, i} ^thousand   →   {0, 1} is the function computed by some satisfiable Boolean formula for which the prover knows that there is an consignment b _ane, b ₂,…, b_grand ∈ {0, one} so that f (b _one, b ₂,…, b_grand )   =   1. Assume that the Boolean formula is given using arbitrary unary and binary Boolean operators. The prover will produce encryptions z _one, z ₂,…, z_k of b _i, b ₂,…, b_g . Then, the prover volition guide the verifier through the encrypted evaluation of the formula, using the Boolean ciphering protocol, one Boolean operator at a time. The event will be a z which is the encryption for the value of f (b _one, b ₂,…, b_k ). And then, the prover opens z and shows the verifier that it encrypts a i.

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